This invention relates to an lithography system particularly usable in the fabrication of integrated circuits from silicon wafers or in printing on various other substrates. It includes improved techniques insuring precise alignment of multiple masks to define circuit or other features on a substrate at various levels or locations of the fabrication process.
The fabrication of integrated circuit electronic devices involves having a series of masks or a series of wafers be successively aligned with respect to each other. To obtain reasonable yields in the manufacture of such devices, precise tolerances are required in the alignment process. For very high-resolution devices, sub-micron alignment tolerances are normally necessary.
The invention utilizes zone plate technology to image alignment patterns in the lithography system with an improved wafer stage subsystem adjustable with respect to registration of such alignment patterns.
It is also desired that the lithography apparatus/system be as compact as possible so as to have the smallest possible "footprint", with attendant savings in clean room space, and to be highly automated. This is accomplished in part by including an improved mask transport system and mask alignment apparatus and incorporating alignment objectives or other image sensing means within a beam column with an improved miniaturized adjusting means affording high resolution.